1. Field of the Invention
This present invention relates to techniques for testing integrated circuits, and, more particularly to “shift mode” and “capture mode” test modes that are currently employed in the integrated circuit industry, particularly for consumer electronics.
2. Description of the Related Art
In the manufacture of integrated circuits, particularly of highly complex integrated circuits, the need arises to perform test operations on the components which constitute the circuit.
Specifically, test techniques are known such as “scan testing”, wherein, instead of performing a functional test at the integrated circuit level, tests are performed aiming at verifying the structure correctness.
In an integrated circuit there may be provided as many as a million flip-flops and more, and the most widespread methods consider the circuit as a group of interconnected functional blocks. This makes it possible, for example, to design components, such as the flip-flops included in a single functional block, in such a way as to allow them to be connected with one another in a so-called scan path in order to undergo testing. Beside the inputs and outputs employed during a normal operation of the circuit, the flip-flops included in such a scan path include, therefore, additional terminals or pins, such as the ones named Scan Input (SI) and Scan Enable input (SE). The flip-flops included in a scan path are connected with their outputs to the SI input of the following flip-flop. The first flip-flop in the path receives an input stimulus from an automatic test unit through an access terminal to the chip of the integrated circuit. The last flip-flop in the scan path gives in turn its output to the automatic test unit through a corresponding test access terminal. Within a single integrated circuit there may be several scan paths.
FIG. 1 of the annexed drawings shows, by way of example, a scan path comprising a plurality of flip-flops 100, 102, 104, . . . (these flip-flops may be present in any rated number). Flip-flop 100 is assumed to be the first flip-flop in the scan path, while flip-flop 104 is considered to be ideally the last flip-flop. Logic blocks 120 are interposed between the individual flip-flops; they are assumed to be interposed between the output Q of the flip-flop upstream and the input D of the flip-flop downstream.
In FIG. 1 there are shown the previously mentioned SI and SE inputs, which are assumed to be ideally connected:                the SI (Scan Input) input to a scan input contact point, and        the SE (Scan Enable) input to a scan enable contact point.        
For the subsequent flip-flops (e.g. flip-flops 102 and 104), while keeping the connection of the SE input to the scan enable contact point, the SI input of the individual flip-flop is connected to the output of the flip-flop upstream. For instance, in the shown example, the SI input of flip-flop 102 is connected to output Q, denoted by 100b, of flip-flop 100, while the SI input of flip-flop 104 is connected to output Q, denoted by 102b, of flip-flop 102. Clock inputs 100a, 102a and 104a are also shown in FIG. 1.
In this respect, it is to be remarked once again that the view in FIG. 1 is deliberately schematic in its essential elements: a scan path of the depicted kind generally comprises a much higher number of mutually cooperating flip-flops.
In particular, in order to perform the scan testing, it is possible to operate according to two different methods, which are known as shift mode and capture mode.
In the shift mode, flip-flops process what they receive at their SI input. The scan enable contact point acts as an interface for the automatic test unit, and allows the test unit to deliver a signal adapted to set the flip-flop into a shift mode.
In the capture mode, the flip-flops process the input signals received on input D, as it happens in the normal operating mode. In various embodiments, in order to shift to the capture mode a low level signal is applied on the SE input of the flip-flop.
What has been said substantially corresponds to operating information and modes which are known in the state of the art, as reported for example in US-A-2006/0075297 (U.S. Pat. No. 7,500,165).
This document acknowledges the fact that the described techniques require the dedication of external pins of the integrated circuit to the scan testing function, in order to allow the connection to the automatic test devices.
Although use is not made of a plurality of external pins dedicated to the test by resorting to the functional pins being shared and having a specific meaning in test mode, in any case the need is felt to limit the number of external pins used; this is due to various different reasons:                a low functional pin count is available,        the necessary hardware for the test should be reduced (channels of the testing device),        with the same number of channels, parallelism (the number of simultaneously tested devices) should be increased, and        generally speaking, it is desirable to minimize the number of external pins dedicated to testing, so as to reduce dimensions and/or to dedicate a higher number of pins to the circuit functions.        
Moreover, the number of internal clocks of an integrated circuit has an impact on the number of external pins. In a currently employed chip there may be as many as hundreds of different “clock domains”, which phrase indicates a set of flip-flops and logic circuits that use the same clock. This fact may cause further difficulties in relation to a possible use of a common gate or a common flip-flop. Actually, there may exist independent clock domains, i.e. clock domains that do not interfere with one another in any way, in a situation wherein the internal clocks supporting them may have different operating frequencies, which fact involves having for each clock domain a respective external pin supporting the testing function. This is a further difficulty as regards the soaring number of test pins.
Specifically, the diagram in FIG. 2 depicts a typical situation where the need exists to handle several internal clocks with different frequencies. These frequencies may correspond, for example, to the operating frequencies of various clock generators, denoted by CK1, CK1′, CK2, CK3, etc.
By way of example and not of limitation of the scope of the present disclosure, generator CK1 may be, for example, a PLL operating at an exemplary frequency of 72 MHz, with an associated divisor by two, which practically acts as a further clock generator CK1′ operating at a frequency of 36 MHz, corresponding to half the frequency generated by generator CK1. Similarly, generator CK2 can be an oscillator of any kind, operating for example at a frequency of 25 MHz, while clock generator CK3 may be an oscillating circuit RC, operating at a frequency of 16 MHz. The reported frequency values obviously have an exemplary value, and the choice of their respective value aims at highlighting that such clock signals and the related clock domains may operate at any frequency, without imposing or assuming any dependence constraint of such frequencies.
FIG. 2 refers mainly to the normal operating mode (without testing) of the device, and highlights the fact that the various clock domains, if necessary, can be “turned off” through clock gating cells 200, integrated in the circuit that must undergo testing.
Cells 200 are subjected to control or enable (EN) signals and can comprise e.g. AND gates with two inputs, which respectively receive:                on one input, the clock signal CK1, CK1′, CK2, CK3, and        on the other input, the EN signal.        
As a consequence, if the EN signal is at level “1”, the clock domain is active, and therefore the clock signal is supplied to flip-flops 100, 102, 104, . . . ; if the EN signal is at level “0”, the clock domain is off.
For the sake of clarity it should be noted that, in the solution considered in FIG. 2, the control or enable signal EN is to be distinguished from the scan enable signal SE.
In order to test the circuit, the structure depicted in FIG. 2 is adapted to be implemented, according to conventional solutions, with two different approaches, that are respectively illustrated in FIG. 3 and in FIG. 4. In these two Figures, parts and components identical or equivalent to parts and components already described with reference to FIGS. 1 and 2 are denoted by the same reference numbers, and the description thereof will be omitted.
Specifically, the solution in FIG. 3 involves the use of plural pins, one for each test clock tst_ck1, tst_ck2, tst_ck3, tst_ck4, in order to solve the set up/hold issue among the various clock domains. Upstream each cell 200, on the input that must receive the clock signal CK1, CK1′, CK2, CK3, a multiplexer 202 is arranged which operates under the control of a test_mode signal. When the test_mode signal shows that the circuit is being tested, multiplexers 202 send, in place of the signal CK1, CK1′, CK2, CK3, a corresponding signal tst_ck1, tst_ck2, tst_ck3, tst_ck4 to the cells 200.
The solution in FIG. 4 involves, on the contrary, the use of a single pin common to all clock domains, on which a test clock signal tst_ck is present. In this case as well, upstream each cell 200, on the input that must receive the clock signal CK1, CK1′, CK2, CK3, a multiplexer 202 is arranged which operates under the control of a test_mode signal. When the test_mode signal indicates that the circuit is being tested, multiplexers 202 send, in place of the signal CK1, CK1′, CK2, CK3, a signal tst_clk to the cells 200. In this case the need arises to handle timing issues among the different clock signals.
The firm Synopsis, Mountain View, Calif., USA offers a software tool that can be used in a design environment for integrated circuits and that is known as DFT_COMPILER. Such a tool includes an application named OCC (On-Chip Clocking) that is adapted to manage various internal clocks of a circuit during a test operation.